Alpha Voiding Control in Soldering

Amit Patel, Matthew Siebenhuhner, Gyan Dutt, Ranjit Pandher, Mitch Holtzer, and T.W. Mok
Alpha Assembly Solutions
South Plainfield, NJ, USA
[email protected]

ABSTRACT

Solder voiding is a common phenomenon across all semiconductor packaging and electronic board assemblies. Voids are a troublesome defect in assemblies created using surface mount technology. Voids can interfere with electric signals, can be insulators when heat dissipation is required, and they can also bethe source of crack propagation and early failure of an assembly when occurring near the pad surface. The acceptable
levels for voiding vary upon on the end-application and environment it’s used in. In the case of thermally demanding harsh environment applications such as automotive and outdoor LED lighting void control is required in order to optimize the performance and extend the lifetime of these components. The lower the voiding on these thermal and electrical pads, the better the connection to the PCB and subsequent layers.

There are many factors that influence void frequency and size. This study focuses on several process, design and materials selection considerations which control or potentially reduce voiding to meet industry and end-market acceptance criteria. More specifically, package design, reflow profiles, and solder
paste chemistry are discussed in the form of application studies. Commercial mid-power PLCC and high-power ceramic LED packages on aluminum metal core PCBs additionally BGA, DPak, and MLF on FR4 PBCs were used for these case studies.

Key words: LED, Voiding, Thermal Management, Lifetime, Reliability, Solder Paste, Alloy, LED Package

INTRODUCTION

The global acceptance of LED-based light sources has propelled the energy efficient technology to enter numerous markets and end applications including high power lighting segments. Examples include exterior automotive headlamps, roadway/street lighting, industrial high bay lights, architectural and entertainment lighting. As a result, customer expectations of maintaining efficiency, government regulations, safety, and reducing overall systems / replacement costs are important to satisfy the adoption rates.

For these high reliability and lifetime requirements, it is critical to have excellent assembly interconnect reliability to address the above needs.

The role of interconnects in LED Level 1 (chip /die attach) and Level 2 (package on board attach) is fundamentally to:
• Convey power and information efficiently and reliably over the rated life.

• Thermal management - get the heat out faster and reliably over the rated life.
• Enable more light output, consistently, for longer time for the same package and system footprint.
• Capable of being processed under robust processing conditions i.e. multiple reflow assembly.

Voids, which are pockets of trapped gasses from solder flux, can cause issues for electric signals, can act as thermal resistors when heat dissipation is required, and they can also be the source of crack propagation and early failure of an assembly. Figure 1 depicts large area voids in the bulk solder layer. The phenomenon of void occurrence is a complex system, there are many factors that drive various levels of voiding. Examples include: chemistry,
reflow profile, volume of material, solderable pad finish and design of the component pads (thermal and electrical).

Figure 1. Voids Entrapment within the Solder Layer

For level 1 LED chip attach assemblies the use of traditional solders can be seen as an advantage from both ease of processing and cost. However, the importance for thermal management is critical for high and ultra-high power LEDs. The junction temperature in the LED increases with increasing drive current. Since more than 50 % of electrical input power is dissipated as heat due to efficiency droop at high drive currents in LEDs, this rise in the junction temperature reduces the light output by increasing the probability of non-radiative recombination causing drop in efficiency and rated lifetime. Therefore, the dissipated heat needs to be removed from the junction in order to maintain the light conversion efficiency and light output from the High Power LED package. The various components in the heat flow path in a High Power LED package are shown in Figure 2.

Figure 2. High Power LED Heat Path.

Additionally for Level 1, the requirements for processing LED packages with solder based die attach on boards as a Level 2 assembly requires multiple soldering reflow capability. With multiple reflows of the same solder bulk layer may increase the levels of voids impacting the overall reliability of the stack at the Level 1 layer.

For Level 2 package on board assemblies LEDs are becoming more integrated with various traditional IC components such as BGAs, D-Paks and MLFs being directly mounted on the same board. This is driven by the need for lighting systems to go beyond general illumination providing more complex features such as control, sensing and modulation. Large area voids can create issues in the electrical signal or generate cracks due to thermal cycling / fatigue thus need for a more robust, low voiding interconnects are required at the Level 2 layer.

EXPERIMENTAL PROCEDURE – DESIGN CASE
There are a variety of LED designs used in the industry ranging from design structure / size and package materials i.e. ceramic and plastic. The goal of this experiment is to observe the effect of voiding based on 3 varying structures with the key difference being the pad geometries. For example, a 2 pad design where the anode and cathode are symmetrical, a 3 pad high aspect ratio design where the central thermal pad is slightly larger in terms of total area and lastly, a 3 pad design where the central thermal pad is significantly larger in terms of total area when compare to the anode and cathode. Table 2 shows the total area and construction of the LED pads.

ASSEMBLY MATERIALS & COMPONENTS Substrate
The substrate used in this study is a custom designed aluminum core PCB. The particular details for this board are shown in Table 1.

1 38–20 Particle size in μm (80% min. between)

Table 1. Test Vehicle Details

LED Components
For this study, three commercially available high power LEDs were selected with varying pad geometries. The parameters for anode, cathode, and thermal pad dimensions for the LEDs are listed in Table 2. All dimensions are in millimeters. The LEDs were chosen to emulate common packages selected in high and ultra-high power assemblies.

Table 2. LED Pad Dimensions (mm)

Solder Pastes
A commercially available no-clean solder paste was used for this study known using a type 41 particle size SAC-based alloy.

PROCESS AND TEST METHOD Equipment Processing Details
Solder paste printing was done using DEK Horizon 03iX printer with a 4 mil thick laser cut stainless steel stencil with a 1 to 1 ratio of aperture size to pad size. Stencil printing parameters used for all solder pastes are shown in Table 3.

Table 3. Print Conditions

Reflow Soldering
The soak reflow profile was used in this study shown in Figure 2 the temperatures are displayed in Table 4.

Figure 2. Reflow Profile, Visual Depiction

Table 4. Reflow Profile used in study

Test Method
To measure and quantify the voiding performance of the varying pastes and LED pad layouts, the assembled and reflowed boards were loaded into an X-ray analysis unit and programmed to quantify the area of each void as a percent of the total pad area and the number of voids under the package.

RESULTS AND DISCUSSION Results
The results of this study are shown in Figure 4.

Figure 4. Percent voiding versus LED package design.

Discussion
From the experimental results, it is evident that solder pad design influences the level of voiding for a given package. The selected packages which have the largest physical difference of pad area and asymmetry in design creates the highest levels of voiding. This is directly related to the total volume of solder deposit for a particular LED package. Table 5 depicts the pad variance for a given design.

Table 5. LED Design Dimensions and Difference in Thermal vs.
Electrical Pads

It is known that having different solder volumes on the same board makes it very difficult to adjust reflow profile setting that balances the activation and evaporation component. A small volume consumes the activator faster than a larger volume which requires a much longer soak profile to remove the diluents / solvents in the flux system.

EXPERIMENTAL PROCEDURE – PROCESS CASE [1]
Adjusting the reflow profile is a very common starting point in order to optimize the level of voiding. In the first set of experiments, multiple solder paste formulations were subjected to various reflow profiles. The profile variations included preheat soaks, and time above liquidus. All reflow profiles were created
using a seven zone convection oven using no nitrogen. An inhouse developed test vehicle, based on a .062 thick FR4 laminate, finished with OSP/Copper pads was used. The test vehicle includes BGA, D-Pak, and MLF devices.

Test Method
Voiding was measured with a Nikon Metrix XT V160 2-D x-ray machine. In each case, altering the profile had an effect on the observed level of voiding. Varying the Preheat Profile Two reflow profiles with different preheat settings. The first is known as a straight ramp profile, where the test vehicle’s surface
temperature increases at a near linear rate of +1.5°C per second up to a peak temperature if 245°C. The second profile has a slightly faster ramp up (+1.56°C/second) to approximately 160°C, then the assembly is allowed to “soak” at temperatures between 160°C and 184°C for approximately 60 seconds, followed by a moderate (0.96°C/second) ramp up to a peak temperature of 240°C.

RESULTS AND DISCUSSION Results
Figure 5 shows the effect the two reflow profiles on a BGA 256 device using one solder paste. Both the solder paste alloy and the BGA spheres were made with SAC 305 alloy.

Figure 5. Voiding Results